By Michiel Steyaert, Arthur H.M. van Roermund, Johan Huijsing
Analog Circuit layout comprises the contribution of 18 tutorials of the 14th workshop on Advances in Analog Circuit layout. each one half discusses a particular todate subject on new and precious layout principles within the quarter of analog circuit layout. every one half is gifted via six specialists in that box and state-of-the-art info is shared and overviewed. This booklet is quantity 14 during this profitable sequence of Analog Circuit layout, offering necessary details and ideal overviews of analog circuit layout, CAD and RF systems.
Analog Circuit layout is a vital reference resource for analog circuit designers and researchers wishing to maintain abreast with the newest improvement within the box. the educational assurance additionally makes it appropriate to be used in a complicated layout course.
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This quantity, drawn from the Circuits and Filters guide, specializes in arithmetic fundamentals; circuit components, units, and their versions; and linear circuit research. It examines Laplace transformation, Fourier tools for sign research and processing, z-transform, and wavelet transforms. It additionally explores community legislation and theorems, terminal and port represetnation, research within the frequency area, and extra.
Additional info for Analog Circuit Design: RF Circuits: Wide band, Front-Ends, DAC's, Design Methodology and Verification for RF and Mixed-Signal Systems, Low Power and Low Voltage
It is ac-coupled using MIM capacitors to the amplifying transistors M1 and M2. Those transistors are operating in class-AB mode. They are respectively biased by nodes DC_N and DC_B, that themselves are determined by a bias current in a diode connected transistor. The bias currents provide on-chip automatic compensation for temperature and process variations. In this way, the variation of the gain over corners and temperature is very limited. The DC operating point is determined by the node DC_CM which is resistively connected to the drains of the amplifying transistors.
The pMOS added current is eliminated by nMOS DC current sources avoiding the current to be amplified to the mixer. A lot of attention has been paid on the matching of these nMOS and pMOS currents. The programmable current amplifier causes some degradation of the linearity, mainly due to the parasitic capacitance in the current mirror which are a consequence of the large size of the transistors. Note that the Early effect is nondominant thanks to the long device lengths used. The third order baseband harmonic is directly up-converted in the mixer to LO3BB.
Plot of the two non-linear currents (above plots) and their sum (bottom plot) in the time domain. The current in the top-most plot depicts the second harmonic component of the non-linear current. Fig. 7. Plot of the two non-linear currents (above plots) and their sum (bottom plot) in the frequency domain. 3. Design measures to decrease the distortion In this section we take a look at different options to decrease the distortion caused by capacitance N1 seen in figure 1. As seen in equation (12) the SFDR in a differential DAC is limited by the third-order distortion and this limit is given by: 52 4 Asw π fRL Ctotal If we want to maximize the SFDR then we have the following options: • decrease the signal frequency • decrease the load resistor RL • decrease the capacitance Ctotal • increase the gain of the switch transistor The first one, decreasing the signal frequency, is not an option.
Analog Circuit Design: RF Circuits: Wide band, Front-Ends, DAC's, Design Methodology and Verification for RF and Mixed-Signal Systems, Low Power and Low Voltage by Michiel Steyaert, Arthur H.M. van Roermund, Johan Huijsing